AUTHORS: Qing K. Zhu
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ABSTRACT: This paper presents the new methodology and CAD programs to detect two serious faults in VLSI design: HV/LV connection faults and floating gate faults. A hierarchical circuit netlist is flattened in order to trace the connectivity of MOS devices in hierarchically designed circuits. Programs were coded in Python and table-look up techniques were used to speed up the program run. Program flows and specification files are discussed. Specification file commands allowed designers to waive non-critical faults after reviewing them in the design. We developed GUI capability for highlighting nets in the schematic window. GUI helps designers review and fix faults in Cadence design environment. Programs and GUI capability have been applied in one industry project.
KEYWORDS: VLSI, Design, Multiple voltages, HV/LV, Floating gate, CAD, Tapeout.
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